The present invention relates in general to memory circuits and, more particularly, to a multiport memory with a write priority detector.
A multiport memory includes three or more read and/or write ports. Each read port and write port includes separate data lines and address lines whereby multiple peripheral devices may independently read from and write to a particular memory cell. For example, a first peripheral device may access physical memory location "0000" through write port 0. A second peripheral device may also access the same memory location "0000" through write port 1. The multiple read ports provide a similar common access to each memory cell. Thus, a multiport memory allows peripheral devices to share physical memory.
One obvious problem with the multiport memory is the write contention possible when two peripheral devices attempt writing to the same memory location simultaneously, or at least during the same write operation. A common solution in the prior art is to perform an address comparison external to the multiport memory and halt the write operation should the write addresses match. Since the address comparison circuitry tends to be complex, and the complexity increases rapidly with more write ports, the multiport memory in the prior art is typically limited to two write ports It is desirable to increase the number of write ports available to allow the multiport memory to interface with more peripheral devices.
Hence, a need exists for a multiport memory capable of internally detecting and resolving address conflicts during write operations without significant loss in system speed or performance.